1. Field of the Invention
The present invention relates to a semiconductor memory cell, a semiconductor memory device, and a method of manufacturing the same, and more particularly, to an electrically erasable and programmable read only memory (EEPROM) cell and an EEPROM device, which have high integration and low source resistance, and a method of manufacturing the same.
2. Description of the Related Art
An EEPROM device is a nonvolatile memory device, which retains stored data even if a power supply is interrupted. The EEPROM device includes a select transistor and a memory transistor, and an EEPROM cell typically includes two EEPROM devices. A pair of EEPROM devices included in a single EEPROM cell has a common source structure in which the EEPROM devices have a single source region in common. In recent years, as the capacitance of a cell memory increases and the demand for high integration is increased, cell size is reduced to produce highly integrated EEPROM devices. However, with the downscaling of cells, the channel length also decreases, thus resulting in some problems such as a short channel effect.
In a conventional EEPROM device, a lightly doped drain (LDD) is typically used as a common source region. However, in an EEPROM that employs an LDD type common source region, the channel length is short with the downscaling of an EEPROM cell, and punch-through occurs in the channel, thereby degrading the stability of the device. In order to prevent punch-through in a channel of an EEPROM device with the LDD type common source region, impurity ions (e.g., boron ions) should be implanted into the device, but this process increases the threshold voltage of the device.
To solve these problems, a method of using a common source region of a double diffused drain (DDD) type in place of the LDD type is proposed. An EEPROM device with a DDD type common source region is structured such that a heavily doped source region is totally surrounded by a lightly doped source region, which has a lower dopant concentration than a lightly doped source region of an LDD type common source region. Thus, even if there is no additional implantation of boron ions, punch-through rarely occurs. However, since the dopant concentration of the lightly doped source region is relatively low, source resistance is increased. The source resistance is further increased in a structure with a long carrier moving path, such as the common source structure. As a result, the electric characteristics of the EEPROM device are degraded.